Semiconductor devices made according to CMOS technology employ complementary insulated-gate field-effect transistors ("FETs"). An advantage of CMOS devices is that insulated-gate FETs individually occupy relatively small chip area and, when arranged in complementary configurations, consume little power. CMOS devices commonly use a power supply voltage of 5 V, especially in digital applications.
A mixed signal integrated circuit is a semiconductor device that contains analog and digital sections. Traditional CMOS technology is generally not suitable for high-quality mixed signal devices due to crosstalk (noise) which occurs between the analog and digital sections. In crosstalk, the effect of actions taking place in one part--e.g., the digital section--of the mixed signal device is partially transmitted through the device substrate and can detrimentally affect actions taking place in another part--e.g., the analog section--of the device. Also, many mixed signal devices need to operate at voltages much greater than 5 V. Accordingly, traditional 5-V CMOS technology is not suitable for high-voltage mixed signal applications.
Bipolar transistors are often combined with FETs to improve overall performance. Bipolar transistors generally respond fast. In addition, bipolar transistors provide readily controllable current gain and high transconductance, both of which are advantageous. Integrating bipolar transistors and FETs into a single integrated circuit permits the high-speed and current-gain features of bipolar transistors to be combined with the low power consumption and high packing density of FETs.
An integrated circuit made according to BiCMOS technology typically combines NPN transistors with complementary insulated-gate FETs. Some BiCMOS devices also contain PNP transistors. In this case, BiCMOS is sometimes referred to as CBiCMOS where the first "C" indicates that complementary bipolar transistors are provided.
The performance improvements available with BiCMOS technology make it attractive for mixed signal integrated circuits, especially those used in high-voltage applications. In high-voltage BiCMOS, some of the transistors handle low-voltage tasks and are not generally suited for high-voltage operation, while other transistors are specially designed to operate at high voltage.
Kosiak et al, U.S. Pat. No. 4,918,026, discloses a method of fabricating high-voltage complementary insulated-gate FETs for a BiCMOS process. The high-voltage FETs in Kosiak et al differ from (standard) low-voltage FETs in that the drains of the high-voltage devices include lightly doped portions which extend under thick portions of the gate dielectric layers. Kosiak et al reports that their high-voltage FETs can tolerate a 30-volt source-drain voltage without incurring avalanche breakdown.
In Kosiak et al, the sources and drains of high-voltage P-channel FETs are formed in N wells provided in a P-type substrate. As a result, the high-voltage P-channel FETs are not resistively connected to the substrate. However, the sources and drains of high-voltage N-channel FETs are formed directly in the P-type substrate. Substantial crosstalk can thus occur between N-channel FETs in one part of the structure and N-channel FETs in another part of the structure.
Mosher et al, U.S. Pat. No. 5,256,582, discloses a CBiCMOS structure that utilizes three epitaxial layers: (a) a lower N-type epitaxial layer, (b) an intermediate P-type epitaxial layer, and (c) an upper N-type epitaxial layer. A P-type buried region lies along the interface between the P-type epi and the lower N-type epi. P-type and N-type buried regions lie along the interface between the upper N-type epi and the P-type epi. An N-type plug, created by implanting an N-type semiconductor dopant into the P-type epi and then thermally driving the implanted dopant, extends fully through the P-type epi to connect the two N-type epis.
Both low-voltage and high-voltage transistors are available in the CBiCMOS structure of Mosher et al. However, it takes 10 hours for Mosher et to drive the N-type plug through the P-type epi. This is a very long time for a commercial fabrication process. It is desirable to have a semiconductor technology which substantially avoids crosstalk, can handle both low-voltage and high-voltage operations, and is suitable for production-scale fabrication.
In addition, a semiconductor technology that combines different types of transistors is difficult to optimize for all the transistors. For example, an integrated circuit having only vertical NPN transistors can be fabricated on a P-doped substrate that helps isolate the NPN transistors from each other. Likewise, an N-type substrate can be conveniently used to achieve transistor isolation in a circuit having only vertical PNP transistors. However, in a circuit that integrates both NPN and PNP transistors, neither a P-type nor an N-type substrate will provide isolation for all the transistors. Further isolation is necessary.
Additional doped regions can be used to provide further PN-junction isolation. But, the capacitances associated with the additional PN junctions reduce transistor speed. Thus, there is also a need for a semiconductor technology which allows NPN and PNP transistors to be integrated with each other and with their FET counterparts, is not highly complex, and provides low capacitances and high transistor speeds while allowing transistors to be isolated from one another.